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  <body><table style="margin: 0 auto;"><tr><td><div class="topbar"><a href="AArch32-regindex.html">AArch32 Registers</a></div></td><td><div class="topbar"><a href="AArch64-regindex.html">AArch64 Registers</a></div></td><td><div class="topbar"><a href="AArch32-sysindex.html">AArch32 Instructions</a></div></td><td><div class="topbar"><a href="AArch64-sysindex.html">AArch64 Instructions</a></div></td><td><div class="topbar"><a href="enc_index.html">Index by Encoding</a></div></td><td><div class="topbar"><a href="ext_alpha_index.html">External Registers</a></div></td><td><div class="topbar"><a href="ext_enc_index.html">External Registers by Offset</a></div></td><td><div class="topbar"><a href="func_index.html">Registers by Functional Group</a></div></td><td><div class="topbar"><a href="notice.html">Proprietary Notice</a></div></td></tr></table><hr/><h1 class="register-section">PRRR, Primary Region Remap Register</h1><p>The PRRR characteristics are:</p><h2>Purpose</h2>
        <p>Controls the top level mapping of the TEX[0], C, and B memory region attributes.</p>
      <h2>Configuration</h2><p>AArch32 System register PRRR bits [31:0] are architecturally mapped to AArch64 System register <a href="AArch64-mair_el1.html">MAIR_EL1[31:0]</a> when EL3 is not implemented or EL3 is using AArch64.</p><p>AArch32 System register PRRR bits [31:0] are architecturally mapped to AArch32 System register <a href="AArch32-mair0.html">MAIR0[31:0]</a> when EL3 is not implemented or EL3 is using AArch64.</p><p>AArch32 System register PRRR bits [31:0] (PRRR_S) are architecturally mapped to AArch32 System register <a href="AArch32-mair0.html">MAIR0[31:0]</a> (MAIR0_S) when EL3 is using AArch32.</p><p>AArch32 System register PRRR bits [31:0] (PRRR_NS) are architecturally mapped to AArch32 System register <a href="AArch32-mair0.html">MAIR0[31:0]</a> (MAIR0_NS) when EL3 is using AArch32.</p><p>This register is present only when EL1 is capable of using AArch32. Otherwise, direct accesses to PRRR are <span class="arm-defined-word">UNDEFINED</span>.</p>
        <p><a href="AArch32-mair0.html">MAIR0</a> and PRRR are the same register, with a different view depending on the value of <a href="AArch32-ttbcr.html">TTBCR</a>.EAE:</p>

      
        <ul>
<li>When it is set to 0, the register is as described in PRRR.
</li><li>When it is set to 1, the register is as described in <a href="AArch32-mair0.html">MAIR0</a>.
</li></ul>
      <h2>Attributes</h2>
        <p>PRRR is a 32-bit register.</p>
      <h2>Field descriptions</h2><h3>When TTBCR.EAE == 0:</h3><table class="regdiagram"><thead><tr><td>31</td><td>30</td><td>29</td><td>28</td><td>27</td><td>26</td><td>25</td><td>24</td><td>23</td><td>22</td><td>21</td><td>20</td><td>19</td><td>18</td><td>17</td><td>16</td><td>15</td><td>14</td><td>13</td><td>12</td><td>11</td><td>10</td><td>9</td><td>8</td><td>7</td><td>6</td><td>5</td><td>4</td><td>3</td><td>2</td><td>1</td><td>0</td></tr></thead><tbody><tr class="firstrow"><td class="lr" colspan="1"><a href="#fieldset_0-31_24">NOS7</a></td><td class="lr" colspan="1"><a href="#fieldset_0-31_24">NOS6</a></td><td class="lr" colspan="1"><a href="#fieldset_0-31_24">NOS5</a></td><td class="lr" colspan="1"><a href="#fieldset_0-31_24">NOS4</a></td><td class="lr" colspan="1"><a href="#fieldset_0-31_24">NOS3</a></td><td class="lr" colspan="1"><a href="#fieldset_0-31_24">NOS2</a></td><td class="lr" colspan="1"><a href="#fieldset_0-31_24">NOS1</a></td><td class="lr" colspan="1"><a href="#fieldset_0-31_24">NOS0</a></td><td class="lr" colspan="4"><a href="#fieldset_0-23_20">RES0</a></td><td class="lr" colspan="1"><a href="#fieldset_0-19_19">NS1</a></td><td class="lr" colspan="1"><a href="#fieldset_0-18_18">NS0</a></td><td class="lr" colspan="1"><a href="#fieldset_0-17_17">DS1</a></td><td class="lr" colspan="1"><a href="#fieldset_0-16_16">DS0</a></td><td class="lr" colspan="2"><a href="#fieldset_0-15_0">TR7</a></td><td class="lr" colspan="2"><a href="#fieldset_0-15_0">TR6</a></td><td class="lr" colspan="2"><a href="#fieldset_0-15_0">TR5</a></td><td class="lr" colspan="2"><a href="#fieldset_0-15_0">TR4</a></td><td class="lr" colspan="2"><a href="#fieldset_0-15_0">TR3</a></td><td class="lr" colspan="2"><a href="#fieldset_0-15_0">TR2</a></td><td class="lr" colspan="2"><a href="#fieldset_0-15_0">TR1</a></td><td class="lr" colspan="2"><a href="#fieldset_0-15_0">TR0</a></td></tr></tbody></table><h4 id="fieldset_0-31_24">NOS&lt;n&gt;, bit [n+24], for n = 7 to 0</h4><div class="field">
      <p>Not Outer Shareable. NOS&lt;n&gt; is the Outer Shareable property for memory attributes n, if the region is mapped as Normal memory that is not Inner Non-cacheable, Outer Non-cacheable, and the appropriate PRRR.{NS0, NS1} field identifies the region as shareable. n is the value of the concatenation of the {TEX[0], C, B} bits from the Translation table descriptor. The possible values of each NOS&lt;n&gt; field other than NOS6 are:</p>
    <table class="valuetable"><tr><th>NOS&lt;n&gt;</th><th>Meaning</th></tr><tr><td class="bitfield">0b0</td><td>
          <p>Memory region is Outer Shareable.</p>
        </td></tr><tr><td class="bitfield">0b1</td><td>
          <p>Memory region is Inner Shareable.</p>
        </td></tr></table><p>The value of this bit is ignored if the region is:</p>
<ul>
<li>Device memory
</li><li>Normal memory that is at least one of:<ul>
<li>Inner Non-cacheable, Outer Non-cacheable.
</li><li>Identified by the appropriate PRRR.{NS0, NS1} field as Non-shareable.
</li></ul>

</li></ul>
<p>The meaning of the NOS6 field is <span class="arm-defined-word">IMPLEMENTATION DEFINED</span>.</p><p>The reset behavior of this field is:</p><ul><li>On a Warm reset, 
      this field resets
       to an architecturally <span class="arm-defined-word">UNKNOWN</span> value.</li></ul></div><h4 id="fieldset_0-23_20">Bits [23:20]</h4><div class="field">
      <p>Reserved, <span class="arm-defined-word">RES0</span>.</p>
    </div><h4 id="fieldset_0-19_19">NS1, bit [19]</h4><div class="field"><p>Mapping of S = 1 attribute for Normal memory regions. This field is used in determining the Shareability of a memory region that is mapped to Normal memory and both:</p>
<ul>
<li>Is not Inner Non-cacheable, Outer Non-cacheable.
</li><li>Has the S bit in the Translation table descriptor set to 1.
</li></ul><table class="valuetable"><tr><th>NS1</th><th>Meaning</th></tr><tr><td class="bitfield">0b0</td><td>
          <p>Region is Non-shareable.</p>
        </td></tr><tr><td class="bitfield">0b1</td><td>
          <p>Region is shareable. The value of the appropriate PRRR.NOS&lt;n&gt; field determines whether the region is Inner Shareable or Outer Shareable.</p>
        </td></tr></table><p>The reset behavior of this field is:</p><ul><li>On a Warm reset, 
      this field resets
       to an architecturally <span class="arm-defined-word">UNKNOWN</span> value.</li></ul></div><h4 id="fieldset_0-18_18">NS0, bit [18]</h4><div class="field"><p>Mapping of S = 0 attribute for Normal memory regions. This field is used in determining the Shareability of a memory region that is mapped to Normal memory and both:</p>
<ul>
<li>Is not Inner Non-cacheable, Outer Non-cacheable.
</li><li>Has the S bit in the Translation table descriptor set to 0.
</li></ul><table class="valuetable"><tr><th>NS0</th><th>Meaning</th></tr><tr><td class="bitfield">0b0</td><td>
          <p>Region is Non-shareable.</p>
        </td></tr><tr><td class="bitfield">0b1</td><td>
          <p>Region is shareable. The value of the appropriate PRRR.NOS&lt;n&gt; field determines whether the region is Inner Shareable or Outer Shareable.</p>
        </td></tr></table><p>The reset behavior of this field is:</p><ul><li>On a Warm reset, 
      this field resets
       to an architecturally <span class="arm-defined-word">UNKNOWN</span> value.</li></ul></div><h4 id="fieldset_0-17_17">DS1, bit [17]</h4><div class="field">
      <p>Mapping of S = 1 attribute for Device memory. From Armv8, all types of Device memory are Outer Shareable, and therefore this bit is <span class="arm-defined-word">RES1</span>.</p>
    <p>The reset behavior of this field is:</p><ul><li>On a Warm reset, 
      this field resets
       to an architecturally <span class="arm-defined-word">UNKNOWN</span> value.</li></ul></div><h4 id="fieldset_0-16_16">DS0, bit [16]</h4><div class="field">
      <p>Mapping of S = 0 attribute for Device memory. From Armv8, all types of Device memory are Outer Shareable, and therefore this bit is <span class="arm-defined-word">RES1</span>.</p>
    <p>The reset behavior of this field is:</p><ul><li>On a Warm reset, 
      this field resets
       to an architecturally <span class="arm-defined-word">UNKNOWN</span> value.</li></ul></div><h4 id="fieldset_0-15_0">TR&lt;n&gt;, bits [2n+1:2n], for n = 7 to 0</h4><div class="field">
      <p>TR&lt;n&gt; is the primary TEX mapping for memory attributes n, and defines the mapped memory type for a region with attributes n. n is the value of the concatenation of the {TEX[0], C, B} bits from the Translation table descriptor. The possible values for each field other than TR6 are:</p>
    <table class="valuetable"><tr><th>TR&lt;n&gt;</th><th>Meaning</th></tr><tr><td class="bitfield">0b00</td><td>
          <p>Device-nGnRnE memory</p>
        </td></tr><tr><td class="bitfield">0b01</td><td>
          <p>Device-nGnRE memory</p>
        </td></tr><tr><td class="bitfield">0b10</td><td>
          <p>Normal memory</p>
        </td></tr></table><p>The value <span class="binarynumber">0b11</span> is reserved. The effect of programming a field to <span class="binarynumber">0b11</span> is <span class="arm-defined-word">CONSTRAINED UNPREDICTABLE</span>.</p>
<p>The meaning of the TR6 field is <span class="arm-defined-word">IMPLEMENTATION DEFINED</span>.</p>
<p>When <span class="xref">FEAT_XS</span> is implemented, stage 1 Inner Write-Back Cacheable, Outer Write-Back Cacheable memory types have the XS attribute set to 0.</p><p>The reset behavior of this field is:</p><ul><li>On a Warm reset, 
      this field resets
       to an architecturally <span class="arm-defined-word">UNKNOWN</span> value.</li></ul></div><div class="access_mechanisms"><h2>Accessing PRRR</h2><p>Accesses to this register use the following encodings in the System register encoding space:</p><h4 class="assembler">MRC{&lt;c&gt;}{&lt;q&gt;} &lt;coproc&gt;, {#}&lt;opc1&gt;, &lt;Rt&gt;, &lt;CRn&gt;, &lt;CRm&gt;{, {#}&lt;opc2&gt;}</h4><table class="access_instructions"><tr><th>coproc</th><th>opc1</th><th>CRn</th><th>CRm</th><th>opc2</th></tr><tr><td>0b1111</td><td>0b000</td><td>0b1010</td><td>0b0010</td><td>0b000</td></tr></table><p class="pseudocode">
if PSTATE.EL == EL0 then
    UNDEFINED;
elsif PSTATE.EL == EL1 then
    if EL2Enabled() &amp;&amp; !ELUsingAArch32(EL2) &amp;&amp; HSTR_EL2.T10 == '1' then
        AArch64.AArch32SystemAccessTrap(EL2, 0x03);
    elsif EL2Enabled() &amp;&amp; ELUsingAArch32(EL2) &amp;&amp; HSTR.T10 == '1' then
        AArch32.TakeHypTrapException(0x03);
    elsif EL2Enabled() &amp;&amp; !ELUsingAArch32(EL2) &amp;&amp; HCR_EL2.TRVM == '1' then
        AArch64.AArch32SystemAccessTrap(EL2, 0x03);
    elsif EL2Enabled() &amp;&amp; ELUsingAArch32(EL2) &amp;&amp; HCR.TRVM == '1' then
        AArch32.TakeHypTrapException(0x03);
    elsif HaveEL(EL3) &amp;&amp; ELUsingAArch32(EL3) then
        if TTBCR.EAE == '1' then
            R[t] = MAIR0_NS;
        else
            R[t] = PRRR_NS;
    else
        if TTBCR.EAE == '1' then
            R[t] = MAIR0;
        else
            R[t] = PRRR;
elsif PSTATE.EL == EL2 then
    if HaveEL(EL3) &amp;&amp; ELUsingAArch32(EL3) then
        if TTBCR.EAE == '1' then
            R[t] = MAIR0_NS;
        else
            R[t] = PRRR_NS;
    else
        if TTBCR.EAE == '1' then
            R[t] = MAIR0;
        else
            R[t] = PRRR;
elsif PSTATE.EL == EL3 then
    if TTBCR.EAE == '1' then
        if SCR.NS == '0' then
            R[t] = MAIR0_S;
        else
            R[t] = MAIR0_NS;
    else
        if SCR.NS == '0' then
            R[t] = PRRR_S;
        else
            R[t] = PRRR_NS;
                </p><h4 class="assembler">MCR{&lt;c&gt;}{&lt;q&gt;} &lt;coproc&gt;, {#}&lt;opc1&gt;, &lt;Rt&gt;, &lt;CRn&gt;, &lt;CRm&gt;{, {#}&lt;opc2&gt;}</h4><table class="access_instructions"><tr><th>coproc</th><th>opc1</th><th>CRn</th><th>CRm</th><th>opc2</th></tr><tr><td>0b1111</td><td>0b000</td><td>0b1010</td><td>0b0010</td><td>0b000</td></tr></table><p class="pseudocode">
if PSTATE.EL == EL0 then
    UNDEFINED;
elsif PSTATE.EL == EL1 then
    if EL2Enabled() &amp;&amp; !ELUsingAArch32(EL2) &amp;&amp; HSTR_EL2.T10 == '1' then
        AArch64.AArch32SystemAccessTrap(EL2, 0x03);
    elsif EL2Enabled() &amp;&amp; ELUsingAArch32(EL2) &amp;&amp; HSTR.T10 == '1' then
        AArch32.TakeHypTrapException(0x03);
    elsif EL2Enabled() &amp;&amp; !ELUsingAArch32(EL2) &amp;&amp; HCR_EL2.TVM == '1' then
        AArch64.AArch32SystemAccessTrap(EL2, 0x03);
    elsif EL2Enabled() &amp;&amp; ELUsingAArch32(EL2) &amp;&amp; HCR.TVM == '1' then
        AArch32.TakeHypTrapException(0x03);
    elsif HaveEL(EL3) &amp;&amp; ELUsingAArch32(EL3) then
        if TTBCR.EAE == '1' then
            MAIR0_NS = R[t];
        else
            PRRR_NS = R[t];
    else
        if TTBCR.EAE == '1' then
            MAIR0 = R[t];
        else
            PRRR = R[t];
elsif PSTATE.EL == EL2 then
    if HaveEL(EL3) &amp;&amp; ELUsingAArch32(EL3) then
        if TTBCR.EAE == '1' then
            MAIR0_NS = R[t];
        else
            PRRR_NS = R[t];
    else
        if TTBCR.EAE == '1' then
            MAIR0 = R[t];
        else
            PRRR = R[t];
elsif PSTATE.EL == EL3 then
    if SCR.NS == '0' &amp;&amp; CP15SDISABLE == Signal_High then
        UNDEFINED;
    elsif SCR.NS == '0' &amp;&amp; CP15SDISABLE2 == Signal_High then
        UNDEFINED;
    else
        if TTBCR.EAE == '1' then
            if SCR.NS == '0' then
                MAIR0_S = R[t];
            else
                MAIR0_NS = R[t];
        else
            if SCR.NS == '0' then
                PRRR_S = R[t];
            else
                PRRR_NS = R[t];
                </p></div><hr class="bottom_line"/><table style="margin: 0 auto;"><tr><td><div class="topbar"><a href="AArch32-regindex.html">AArch32 Registers</a></div></td><td><div class="topbar"><a href="AArch64-regindex.html">AArch64 Registers</a></div></td><td><div class="topbar"><a href="AArch32-sysindex.html">AArch32 Instructions</a></div></td><td><div class="topbar"><a href="AArch64-sysindex.html">AArch64 Instructions</a></div></td><td><div class="topbar"><a href="enc_index.html">Index by Encoding</a></div></td><td><div class="topbar"><a href="ext_alpha_index.html">External Registers</a></div></td><td><div class="topbar"><a href="ext_enc_index.html">External Registers by Offset</a></div></td><td><div class="topbar"><a href="func_index.html">Registers by Functional Group</a></div></td><td><div class="topbar"><a href="notice.html">Proprietary Notice</a></div></td></tr></table><p class="versions">30/03/2023 19:06; 997dd0cf3258cacf72aa7cf7a885f19a4758c3af</p><p class="copyconf">Copyright © 2010-2023 Arm Limited or its affiliates. All rights reserved. This document is Non-Confidential.</p></body>
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